# This parameter points to the library that contains information on the logic gates in the synthesis technology library. # Implementation for standard operators, such as +, * In other words, the tool during synthesis maps a design to the logic cells present in this library. # The parameter specifies the file that contains all the logic cells that should used for mapping during synthesis. # This parameter is used to specify the synthesis tool all the paths that it should search when looking for a synthesis technology library for reference during synthesis. Set stdcellhome /sim/synopsys/SAED_EDK90nm/Digital_Standard_Cell_Library/ # set designDB /proj/arcade/synopsys/SAED32_EDK/lib/stdcell_rvt/db_ccs/saed32rvt_tt1p05v25c.db # set designDB /vlsidl/dk/TSMC/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/CCS/tcbn65gplus_140b/tcbn65gplustc.db Set designDB /sim/synopsys/SAED_EDK90nm/Digital_Standard_Cell_Library/synopsys/models/saed90nm_typ.db
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